In a semiconductor device, a shallow trench isolation (STI) method of burying an insulator in a trench formed in a semiconductor substrate is generally used as a method of electrically isolating elements such as transistors, diodes, trench capacitors, or resistors provided over the semiconductor substrate.
The STI method is known to be capable of achieving a desired element withstand voltage. The STI method is described with reference to the drawings.
FIGS. 1A to 1F are schematic sectional views of a principal portion, illustrating a method of manufacturing a semiconductor device. As shown in FIG. 1A, a silicon oxide film 200 and a silicon nitride film 300 are formed over a semiconductor substrate 100 and then patterned.
As shown in FIG. 1B, the semiconductor substrate 100 is etched using the silicon nitride film 300 as a mask to form trenches 101. Each of the trenches 101 has a flat bottom 101a. 
The angle formed by the bottom and the side of each trench 101 is referred to as a “taper angle α”.
As shown in FIG. 1C, silicon oxide films 101b are formed over the inner walls of the trenches 101 by surface thermal oxidation. Then, oxide films 400 are formed in the trenches 101 by chemical vapor deposition (CVD) and polished by chemical mechanical polishing (CMP). The material of the oxide films 400 is a silicon oxide film.
As shown in FIG. 1D, the silicon nitride film 300 and the silicon oxide film 200 are removed by chemical treatment or isotropic etching.
As shown in FIG. 1E, p-type metal oxide semiconductor (PMOS) regions 102 and n-type metal oxide semiconductor (NMOS) regions 103 are formed by well implantation. Further, channel regions 104 and 105 are formed by channel implantation.
As shown in FIG. 1F, a gate oxide film 106 is formed over each of the PMOS regions 102 and the NMOS regions 103, and gate electrodes 107 and 108 are then formed. Further, source and drain regions 109a, 109b, 110a, and 110b are formed over the semiconductor substrate 100 to form MOS transistors 111 and 112.
When the trenches 101 are formed in the semiconductor substrate 100 by the STI method, a semiconductor device 113 having isolated element regions is manufactured. The trench width decreases with increasing in integration of a semiconductor device. Therefore, even when the trench width is narrowed, it is necessary to achieve sufficient element withstand voltage.
The term “element withstand voltage” represents a voltage difference between the source region 109b and drain region 110a when a specified current flows between the source and drain regions 109b and 110a with each trench 101 provided therebetween as shown in FIG. 1F. A semiconductor device preferably has a higher withstand voltage.